Apple’s next-generation A20 Pro system-on-chip will enhance AI processing capabilities through a significant upgrade to its memory architecture, opting for six-channel LPDDR5X RAM with a 96-bit bus width instead of adopting the newer LPDDR6 standard. This move marks a departure from Apple’s previous reliance on 4-channel, 64-bit memory configurations, aiming to address data bottlenecks common in on-device AI tasks.
The adoption of six-channel memory improves the chip’s maximum bandwidth, allowing the A20 Pro to manage intensive AI workloads more efficiently. The increased bus width reduces the risk of the processor idling while waiting for data, which has been a limiting factor in earlier designs. These details come as part of new schematics linked to Apple’s first 2nm fabrication process, revealing a broader memory interface tailored to AI performance demands.
Complementing the memory upgrade, Apple has transitioned from the older inFO-PoP packaging method to Wafer-Level Multi-Chip Module (WMCM) packaging. This shift separates the DRAM from the main chip die, improving heat dissipation and sustaining high performance over prolonged AI operations. Better thermal management is crucial for maintaining consistent processing speeds when running complex neural engine tasks.
While the A20 Pro will not incorporate LPDDR6 RAM—a standard supported by competitors like Snapdragon 8 Elite Gen 6 Pro—Apple offsets this by expanding memory channels and tweaking the system design to maximize bandwidth. This strategy underlines Apple’s long-standing approach of delaying adoption of new memory standards but compensating with architectural innovations tailored to their specific performance goals.